In a source synchronous data communication scheme for chip-to-chip communication, a clock signal for the data is transmitted along with the data. This may also be referred to as a forwarded clock scheme, and is illustrated at a high level of abstraction in FIG. 1. FIG. 1 illustrates the transfer of data signals and a clock signal from chip 102 to chip 104 via transmission lines 106 for the data signals, and transmission line 110 for the clock signal.
For simplicity, the data signals and clock signal are indicated as single-ended, but in other implementations, these signals may be differential signals. For example, a differential forwarded clock signal may be propagated, and the data signals may be differential. Some of these data signals may be error correction signals to provide error detection or error correction capability.
System clock 112 provides a clock signal to PLL (Phase Locked Loop) 114 on chip 102, and to PLL 116 on chip 104, so that a global clock may be generated for chips 102 and 104, as indicated by core clocks 118 and 120. Data signals are generated by core logic 122 on chip 102, and received data is made available to core logic 124 on chip 104. The data generated by core logic 122 is clocked into registers, or sets of flip-flops, 126, and the transmitters 128 transmit the data signals over transmission lines 106 to chip 104. Registers 126 are clocked by PLL 114, and PLL 114 also provides the forwarded clock signal to transmitter 130 for propagation over transmission line 110 to chip 104.
The data signals are received by data receivers 132. A typical data receiver 132 comprises amplifier 134 and register 136 for sampling the received data signal, and comprises PI (Phase Interpolator) 138 to provide a sampling clock signal to register 136. The forwarded clock signal is received and amplified by FCA/DCC (Forward Clock Amplifier/Duty Cycle Correction). The DCC functional unit is included in FCA/DCC because for differential signaling, the data is sampled on the rising and falling transitions of the differential forwarded signal, so that duty cycle correction should be performed to maintain a 50% duty cycle.
SBDLL (Self-Biased Delay Locked Loop) provides multiple clock signals at different relative phases, all generated from the amplified forwarded clock signal provided by FCA/DCC. For example, SBDLL may provide eight clock signals, each having a relative phase of 2 πn/8 radians, where n=0,1, . . . , 7. These multiple clock signals are provided to PI 138. Each PI 138 is adjusted via one or more control loops (not shown) to further interpolate among the multiple clock signals provided by SBDLL, with the goal of clocking their respective register 136 at the center of their respective data eye. For example, each PI 138 may provide a clock signal having any one of 64 phases. As a particular example, any two clock signals provided by SBDLL differing by π/4 radians may be interpolated so that any one of eight clock signals may be generated by PI 138, where the eight clock signals so generated are uniformly spaced in phase between the two selected clock signals from SBDLL. For differential signaling, the multiple clock signals provided by SBDLL are differential in nature.
Circuit blocks FCA/DCC and SBDLL, and receivers 132 in FIG. 1 are usually connected directly to a single power supply (not shown) providing a supply voltage VCC. However, noise on the power supply rail VCC may produce phase jitter in the various generated clock signals, and may prevent the system from transmitting data at sufficiently high rates. Furthermore, SBDLL may output up to eight high speed clock signals, and in some applications, these eight high speed clock signals may be distributed to forty phase interpolators for 20 data lanes. It is difficult to match the clock routings due to layout errors, as well as systematic and random variations in the manufacturing process. As a result, the multiple clock signals generated by SBDLL may not have the uniformly spaced phase differences as desired. Also, distributing up to eight clock signals over several thousands of microns may generate noise in the power supply rail, thereby further contributing to phase jitter.